library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

-- synopsys translate_off
-- synthesis translate_off
--library csx_HRDLIB_FTSM;
-- use csx_HRDLIB_FTSM.VCOMPONENTS.all;
-- synthesis translate_on
-- synopsys translate_on

library work;
 use work.router_pack.all;


-------------------------------------------------------------------------------
entity msl_ip is
-------------------------------------------------------------------------------
port( 
      -- General Control: --
      RESET     : in  std_logic;  -- Active  

      -- External input i/f: --
      RI        : in  std_logic;
      AI        : out std_logic;
      DATAI     : in  std_logic_vector(vc_width+msl_ind_width+flit_width_con-1 downto 0);

      -- Internal output i/f: --
      RO_H_ARR  : out signaling_msl_bus_type;  -- SL x VC x NumOfPorts
      RO_BT_ARR : out signaling_msl_bus_type;  -- SL x VC x NumOfPorts -- BT can be also broadcasted as DATA!
      AO_ARR    : in  signaling_msl_bus_type;  -- SL x VC x NumOfPorts -- Acknowelege can be ORed sinceonly one OP will return acknowelege to the certain VC.

      DO        : out data_msl_bus_type        -- SL x VC x flit_width (the data is connected directly to all OP-VCs)
);           
-------------------------------------------------------------------------------
end msl_ip ;
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
architecture msl_ip_arch of msl_ip is
-------------------------------------------------------------------------------

component ssl_ip_top
port( 
      -- General Control: --
      RESET     : in  std_logic;  -- Active  

      -- External input i/f: --
      RI        : in  std_logic;
      AI        : out std_logic;
      DATAI     : in  std_logic_vector(flit_width_con-1 downto 0);

      -- Internal output i/f: --
      RO_H_ARR  : out std_logic_vector(num_of_ports_con-1 downto 0); -- NumOfPorts 
      RO_BT_ARR : out std_logic_vector(num_of_ports_con-1 downto 0); -- NumOfPorts
      AO_ARR    : in  std_logic_vector(num_of_ports_con-1 downto 0); -- NumOfPorts

      DO        : out std_logic_vector(flit_width_con-1 downto 0)    -- one bus is broadcasted to all ports of the same SL
);           
end component;

type ext_if_type is array (0 to num_of_sl_con-1) of std_logic_vector(num_of_vc_con-1 downto 0);
signal ri_arr, ai_arr : ext_if_type;  -- SL x VC 

signal datai0_not, datai1_not : std_logic;
signal flit_type : std_logic_vector(2 downto 0);

begin

msl_ip_gen: for i in 0 to (num_of_sl_con-1) generate

 msl_ip_v_gen: for j in 0 to (num_of_vc_con-1) generate

  u_ssl_ip_top: ssl_ip_top
  port map( 
      RESET     => RESET,    

      RI        => ri_arr(i)(j),
      AI        => ai_arr(i)(j),
      DATAI     => DATAI(flit_width_con-1 downto 0), -- input data wired to all IP-VCs

      RO_H_ARR  => RO_H_ARR(i)(j), -- connected to all SSL-OPs of the same SL (#of ports x #VC)
      RO_BT_ARR => RO_BT_ARR(i)(j),
      AO_ARR    => AO_ARR(i)(j),

      DO        => DO(i)(j)
  );

 end generate; -- j
end generate;  -- i

flit_type <= DATAI(flit_v_format_h) & DATAI(flit_sl_format_h) & DATAI(flit_sl_format_l);

ri_arr(0)(0) <= RI when (flit_type="000") else '0'; -- VC=0, SL=00 
ri_arr(0)(1) <= RI when (flit_type="100") else '0'; -- VC=1, SL=00
ri_arr(1)(0) <= RI when (flit_type="001") else '0'; -- VC=0, SL=01
ri_arr(1)(1) <= RI when (flit_type="101") else '0'; -- VC=1, SL=01
ri_arr(2)(0) <= RI when (flit_type="010") else '0'; -- VC=0, SL=10
ri_arr(2)(1) <= RI when (flit_type="110") else '0'; -- VC=1, SL=10
ri_arr(3)(0) <= RI when (flit_type="011") else '0'; -- VC=0, SL=11
ri_arr(3)(1) <= RI when (flit_type="111") else '0'; -- VC=1, SL=11

AI <= ai_arr(0)(0) or ai_arr(0)(1) or ai_arr(1)(0) or ai_arr(1)(1) or
      ai_arr(2)(0) or ai_arr(2)(1) or ai_arr(3)(0) or ai_arr(3)(1);

-------------------------------------------------------------------------------
end msl_ip_arch;
-------------------------------------------------------------------------------                 

   
-------------------------------------------------------------------------------
configuration  msl_ip_cfg  of msl_ip is
-------------------------------------------------------------------------------
   for msl_ip_arch
   end for;
-------------------------------------------------------------------------------
end  msl_ip_cfg;              
-------------------------------------------------------------------------------
                 
